By TSMC (Taiwan Semiconductor Manufacturing Company)
CoWoS®-L advanced packaging service enables larger high-performance computing (HPC) products by combining Chip on Wafer on Substrate with RDL-based interposer, higher density embedded local silicon interconnect (LSI), eDTC, and the integration of diverse embedded chips. TSMC’s first CoWoS®-L at 3.5X-reticle size has been in volume production since 2024. To meet the escalating demand for higher package performance and artificial intelligence (AI) computing power, CoWoS®-L continues scaling the interposer size to integrate more silicon and memory in CoWoS®. CoWoS®-L features include: 1. LSI chips for a high routing density die-to-die interconnect through multiple layers of sub-micron copper lines. LSI chips can feature a variety of connection architectures, e.g., System-on-Chip (SoC)-to-SoC, SoC-to-chiplet, SoC-to-high-bandwidth memory (HBM), within each product, and can be used repeatedly in multiple products. The corresponding metal types, layer counts, and pitches align with the offering from CoWoS®-S. 2. A molding-based interposer with a wide pitch of RDL layers on the front-side and back-side that delivers signal and power provides a low loss of high frequency signals during high-speed transmission. 3. The ability to integrate additional elements, such as stand-alone eDTCs underneath the SoC die to improve power management.
