By ASML
The PAS 5500/100D i-line stepper is designed for mass production at 0.4 μm and achieves extremely high throughput while maintaining the utmost versatility with its variable Numerical Aperture (NA). This stepper extends i-line’s capability for manufacturing multiple generations of sub-half-micron design rules by optimizing both depth of focus and resolution for critical process layers. Technical Specifications Lens Wavelength: 365 nm NA: 0.48—0.60 (variable) Resolution: 0.40 μm Field size, for reticle with pellicle - Diameter: 31.1 mm - Max X: 22.0 mm - Max Y: 27.4 mm Usable depth of focus: ≥ 1.1 μm - Distortion: ≤ 60 nm Overlay 99.7% with 2 pt. Global Alignment: < 60 nm Production Throughput With field-by-field leveling, 200-mJ/cm 2 dose and at specified overlay accuracy - 150-mm wafers, 40 shots: ≥ 100 wph - 200-mm wafers, 70 shots: ≥ 72 wph Illumination Intensity: ≥ 900 mW/cm 2 Uniformity: ≤ 1.5% Variable coherence range: σ = 0.3—0.7 Key Features and Benefits - Automated Variable-NA i-Line Projection Lens: Lens technology allowing 0.40-μm imaging. - Completely redesigned variable partial Coherence Illuminator: 1.5-kW illuminator power results in 900 mW/cm 2 at wafer level. - Broadband Field-by-field Focus Leveling System: Leveling while moving from one site to another. - Advanced Light-weight Stage: High precision combined with high throughput. - Direct Reticle-Referenced, Through-The-Lens (TTL) Phase-Grating Alignment: Optimum overlay and matching. - Built-In CLASS 1 Laminar Airflow: Enhances interferometer stability, provides ultra-clean wafer environment.
For today’s advanced microchips, defects as small as a couple of nanometers can render the entire chip useless. With its 1-nanometer resolution, e-beam inspection offers just the right kind of eyes to spot those tiny misprints. ASML is at the forefront of developments in e-beam metrology and inspection. E-beam achieves a higher resolution than YieldStar, but it measures more slowly, which means that it’s typically used after the pattern is etched onto the wafer. ‘E’ is for ‘electron’ E-beam technology has been around for decades. The basic concept is that a metal wire is heated until it gives off electrons, which are accelerated and formed into a beam by electric and magnetic fields. Unlike visible and ultraviolet light (but just like extreme ultraviolet light) electron beams must travel in a vacuum so they are not deflected or absorbed before reaching the target. In metrology and inspection in the semiconductor industry, the e-beam scans across the wafer. The electrons strike the surface and penetrate a small distance into the material, generating new 'secondary electrons' before being scattered. Just as with diffraction-based measurements, measuring the scattering of secondary electrons allows us to build up a very high-resolution picture of the surface. The more focused the beam, the smaller the details that can be measured. Speeding up e-beam imaging The tricky thing with e-beam measurements is that they’re quite slow. As a result, they have only typically been used in the early R&D phase of chip manufacturing, where time is less of an issue. ASML is leading the way in speeding up e-beam measurements so that manufacturers can enjoy their benefits in volume production. One way we do that is by developing solutions that focus e-beam measurements on specific hotspots where defects are more likely or more critical. In-line wafer and reticle inspection By speeding up the process and narrowing down the search to specific areas, e-beam can be used directly in the production line for wafer inspection while maintaining productivity levels.
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By autumn 2003, the immersion team was able to demonstrate concrete imaging results on the ASML prototype system dubbed the TWINSCAN AT:1150i. "The proto results changed the lithography roadmap almost instantly," Jan says. "We defined a series of new lithography systems in a very short period of time that would directly address the chip industry's resolution struggle."
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Using the vast amounts of data generated by our systems, computational lithography simulates the manufacturing process with powerful algorithms. These simulations help to design a chip blueprint (the reticle) that contains the pattern to be printed on the wafer. That's how we make sure that our lithography machines print what they should. This technique is called optical proximity correction (OPC) and is often combined with specific illumination optimizations in the lithography system. ASML's industry-leading computational lithography products enable accurate lithography simulations that help to improve chip yield and quality.
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