By ASML
In-scanner metrology Precision and speed are paramount for today’s advanced chipmaking machines. But sub-nanometer inaccuracies inevitably creep in due to material imperfections, temperature fluctuations and atmospheric pressure changes. Scanner metrology software uses computational models of machine processes in machines to predict and coordinate how the powerful mechatronic modules within our lithography systems should behave to compensate for physical imperfections and maximize system performance. Everything counts A lithography system (scanner) must work 24/7 with sub-nanometer precision, while accelerating mechatronic modules at incredible speeds. For example, the reticle stage accelerates at close to 16g and the wafer stage to 7g. That’s more acceleration than a jet fighter. It’s not possible to mechanically construct a machine capable of this level of alignment and precision, accelerating at those speeds, and with the level of reliability and repeatability required to make today’s computer chips without the help of in-scanner metrology. Chip by chip adjustments Lithography systems are the most ‘tweakable’ tool in the chipmaking process. There are a multitude of ‘knobs’ within the system that can be used to make small adjustments specific to each individual chip on each wafer. By constantly measuring the behavior of the lithography system, in-scanner metrology is used to calculate and then coordinate the many tiny adjustments that need to be made by the physical components (the ‘knobs’) to optimize the pattern on every microchip. Hundreds of sensors, including position, temperature, energy and motion sensors, measure every aspect within the system. Advanced algorithms are used to interpret these large volumes of data and coordinate the necessary tweaks in very minor but detailed ways, at the sub-nanometer scale, using thousands of actuators. Enabling 3D chip architecture In-scanner metrology plays a particularly critical role in ensuring the quality of a certain type of memory chip, known as 3D NAND. These are the flash memory chips used in SD cards, solid state hard drives and smartphones. Previously made in 2D, the introduction of 3D technology was a game-changer for memory chips. Stacking memory cells on top of each other greatly increases storage and enables the chips to run more efficiently and use less energy. But these chips are complex to make and a challenge to measure. 3D NAND chipmakers have to fabricate the intricate structures found on a 2D chip, and then line them up in the vertical plane, connecting them using tiny vertical channels. Many metrology systems can’t penetrate these 3D structures to look inside the chip to detect fabrication issues, so production relies heavily on in-scanner metrology software to optimize quality. By analyzing the vast amount of data generated while layers are added in the lithography system, the software feeds this back to optimize alignment and overlay.
For today’s advanced microchips, defects as small as a couple of nanometers can render the entire chip useless. With its 1-nanometer resolution, e-beam inspection offers just the right kind of eyes to spot those tiny misprints. ASML is at the forefront of developments in e-beam metrology and inspection. E-beam achieves a higher resolution than YieldStar, but it measures more slowly, which means that it’s typically used after the pattern is etched onto the wafer. ‘E’ is for ‘electron’ E-beam technology has been around for decades. The basic concept is that a metal wire is heated until it gives off electrons, which are accelerated and formed into a beam by electric and magnetic fields. Unlike visible and ultraviolet light (but just like extreme ultraviolet light) electron beams must travel in a vacuum so they are not deflected or absorbed before reaching the target. In metrology and inspection in the semiconductor industry, the e-beam scans across the wafer. The electrons strike the surface and penetrate a small distance into the material, generating new 'secondary electrons' before being scattered. Just as with diffraction-based measurements, measuring the scattering of secondary electrons allows us to build up a very high-resolution picture of the surface. The more focused the beam, the smaller the details that can be measured. Speeding up e-beam imaging The tricky thing with e-beam measurements is that they’re quite slow. As a result, they have only typically been used in the early R&D phase of chip manufacturing, where time is less of an issue. ASML is leading the way in speeding up e-beam measurements so that manufacturers can enjoy their benefits in volume production. One way we do that is by developing solutions that focus e-beam measurements on specific hotspots where defects are more likely or more critical. In-line wafer and reticle inspection By speeding up the process and narrowing down the search to specific areas, e-beam can be used directly in the production line for wafer inspection while maintaining productivity levels.
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By autumn 2003, the immersion team was able to demonstrate concrete imaging results on the ASML prototype system dubbed the TWINSCAN AT:1150i. "The proto results changed the lithography roadmap almost instantly," Jan says. "We defined a series of new lithography systems in a very short period of time that would directly address the chip industry's resolution struggle."
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Using the vast amounts of data generated by our systems, computational lithography simulates the manufacturing process with powerful algorithms. These simulations help to design a chip blueprint (the reticle) that contains the pattern to be printed on the wafer. That's how we make sure that our lithography machines print what they should. This technique is called optical proximity correction (OPC) and is often combined with specific illumination optimizations in the lithography system. ASML's industry-leading computational lithography products enable accurate lithography simulations that help to improve chip yield and quality.
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