The foundation of the NanoSOI fabrication process is the device layer. Photonic waveguides capable of light propagation are patterned using 100 keV electron beam lithography technology. Fully-etched devices (etched down to the buffer oxide, as shown in the above diagram) are created using an e-beam mask material and anisotropic ICP-RIE etching process. The minimum feature size is 120 nm and the minimum feature spacing is 120 nm, where duty cycle of surrounding region is ≤ 50%. For duty cycles greater than 50%, resolution will decrease further because of proximity effects. Silicon Nitride Substrate Specifications - Device Layer Type: Silicon nitride (Si x N y) - Device Layer Thickness: 400 nm - Buffer Oxide Layer Thickness: 4.5 μm - Silicon Handle (Substrate) Thickness: 525 μm - Wafer Manufacturer: Applied Nanotools fabricates the Si x N y on WaferPro wafers Propagation Loss Measurements: Applied Nanotools and its collaborators measure the optical propagation loss using microring resonators and extracting the round-trip loss from the measured optical spectra. The latest propagation loss results for fully-etched 400 nm silicon nitride waveguides is listed in the table below (publication of detailed data is pending): - 0.75 μm waveguide width: 0.8 dB/cm at 1310 nm, 1.2 dB/cm at 1550 nm - 1 μm waveguide width: N/A at 1310 nm, 1.0 dB/cm at 1550 nm Proximity Effects: A limitation of electron beam lithography technology is electron scattering effects when exposing patterns into the mask. During the file preparation process, we apply a proximity effect correction algorithm to the design to mitigate these effects. However, extreme cases such as large areas/pads (> 10 × 10 μm) in close proximity to high-resolution features or small feature spacings are difficult to correct for. Please inquire with us if your design has large areas to be exposed in conjunction with high resolution features or small spacings. For regions with duty cycle (pattered area ÷ total area) larger than 50%, the minimum dimension and minimum spacing will be larger than what is specified in the design rules. The examples below show acceptable designs (green check mark) and designs with duty cycles greater than 50% (red X). Sidewall Angle: Imperfections in the mask and the etching process will create an angle to the sidewall of the waveguide. As of November 2025, the sidewall angle of silicon nitride waveguides fabricated with our process is approximately 90 ± 2 degrees (improved from 83.5 degrees). The angle is also dependent on the density of the features and may vary slightly in areas with small gaps between features. We aim to have the waveguide dimensions match the GDS design with proximity and etch bias corrections applied during layout processing.
