The following table summarizes the design rules for each layer available in the NanoSOI Silicon Nitride MPW runs: Layer Number: 4 Process: Silicon nitride full etch Minimum Feature Size: 120 nm Minimum Feature Spacing: 120 nm Design Area: 9 mm x 9 mm Notes: Feature sizes specified where duty cycle of surrounding region is ≤ 50%. Layer Number: 6 Process: Through-cladding windows Design Area: Standard layout is 9 x 9 mm. Deep trench layout is 8.78 x 8.78 mm Notes: Requires prior approval to use. Please inquire with Support two weeks before MPW deadline. Layer Number: 11 Process: Tri-layer metal: TiW alloy Minimum Feature Size: 5 μm Minimum Feature Spacing: 5 μm Design Area: Standard layout is 9 x 9 mm. Deep trench layout is 8.745 x 8.745 mm Layer Number: 12 Process: Tri-layer metal: TiW/Au Bilayer Minimum Feature Size: 10 μm Minimum Feature Spacing: 10 μm Design Area: Standard layout is 9 x 9 mm. Deep trench layout is 8.745 x 8.745 mm Layer Number: 13 Process: Tri-layer metal: Bond pad open Minimum Feature Size: 10 μm Minimum Feature Spacing: 10 μm Design Area: Standard layout is 9 x 9 mm. Deep trench layout is 8.745 x 8.745 mm Notes: Must be placed over Layer 12 and smaller than Layer 12 by 5 μm. Layer Number: 189 Process: Custom dicing Minimum Feature Size: 100 μm Minimum Feature Spacing: 3 mm Design Area: 9 mm x 9 mm Notes: 50 μm spacing to devices. Layer Number: 200 Process: SEM imaging Minimum Feature Size: 500 nm wide Minimum Feature Spacing: None Design Area: 9 mm x 9 mm Notes: Only rectangular boxes with aspect ratio 4:3 (width to height). Layer Number: 201 Process: Deep trench Minimum Feature Size: 260 μm Minimum Feature Spacing: 3 mm Design Area: 8.78 mm x 8.78 mm Notes: 35 μm spacing to metal. Only extend Layer 4 edge couplers into Layer 201. Layer Number: 202 Process: Deep trench exclusion layer Minimum Feature Size: 3 mm x 200 μm Minimum Feature Spacing: 3 mm Notes: Required for deep trench layouts. Exclusion layer to allow for chip handling. Layer Number: 203 Process: Thermal isolation trenches Minimum Feature Size: 30 μm Minimum Feature Spacing: 35 μm Design Area: 8.78 mm x 8.78 mm Notes: 35 μm spacing to metal. 30 μm spacing to silicon nitride. Layer Number: 998 Process: Dream Photonics FaML (reserved) Design Area: 8.78 mm x 8.78 mm Notes: May only be used for Dream Photonics black box cells. White box cell replacement by ANT is only available for FaML cells. Please inquire with Support two weeks before MPW deadline. The image above shows the correlation of the layer numbers to each physical layer in the fabrication process. Design examples for deep trench, thermal isolation trenches, and the SEM imaging layer are also available.
