Design rules for each layer available in the NanoSOI Silicon MPW runs. Layer 1: Silicon full etch. Minimum feature size 60 nm lines. Minimum feature spacing 70 nm lines. Design area 9 mm x 9 mm. Feature sizes specified where duty cycle of surrounding region is ≤ 50%. Layer 1: Silicon full etch IF both air cladding and deep trench are required. Minimum feature size 100 nm lines. Minimum feature spacing 100 nm lines. Design area 9 mm x 9 mm. If air cladding and deep trench are required, the silicon feature size increases to improve yield. Layer 5: Direct metallization. Minimum feature size 5 μm. Minimum feature spacing 10 μm. Design area: Standard layout is 9 x 9 mm. Deep trench layout is 8.745 x 8.745 mm. Requires prior approval to use. Please inquire with Support two weeks before MPW deadline. Layer 6: Through-cladding windows. Design area: Standard layout is 9 x 9 mm. Deep trench layout is 8.78 x 8.78 mm. Requires prior approval to use. Please inquire with Support two weeks before MPW deadline. Layer 11: Tri-layer metal: TiW alloy. Minimum feature size 3 μm. Minimum feature spacing 3 μm. Design area: Standard layout is 9 mm x 9 mm. Deep trench layout is 8.745 mm x 8.745 mm. Layer 12: Tri-layer metal: TiW/Au Bilayer. Minimum feature size 5 μm. Minimum feature spacing 8 μm. Design area: Standard layout is 9 mm x 9 mm. Deep trench layout is 8.745 mm x 8.745 mm. Layer 13: Tri-layer metal: Bond pad open. Minimum feature size 10 μm. Minimum feature spacing 10 μm. Design area: Standard layout is 9 mm x 9 mm. Deep trench layout is 8.745 mm x 8.745 mm. Must be placed over Layer 12 and smaller than Layer 12 by 5 μm. Layer 189: Custom dicing. Minimum feature size 100 μm. Minimum feature spacing 3 mm. Design area 9 mm x 9 mm. 50 μm spacing to devices. Layer 200: SEM imaging. Minimum feature size 500 nm wide. Design area 9 mm x 9 mm. Only rectangular boxes with aspect ratio 4:3 (width to height). Layer 201: Deep trench. Minimum feature size 260 μm. Minimum feature spacing 3 mm. Design area 8.78 mm x 8.78 mm. 35 μm spacing to metal. Only extend Layer 1 edge couplers into Layer 201. Layer 202: Deep trench exclusion layer. Minimum feature size 3 mm x 200 μm. Minimum feature spacing 3 mm. Required for deep trench layouts. Exclusion layer to allow for chip handling. Layer 203: Thermal isolation trenches. Minimum feature size 15 μm. Minimum feature spacing 15 μm. Design area 8.78 mm x 8.78 mm. 15 μm spacing to metal. 10 μm spacing to silicon. Layer 998: Dream Photonics FaML (reserved). Design area 8.78 mm x 8.78 mm. May only be used for Dream Photonics black box cells. White box cell replacement by ANT is only available for FaML cells. Please inquire with Support two weeks before MPW deadline. The image above shows the correlation of the layer numbers to each physical layer in the fabrication process. A layer definition file containing the NanoSOI layer information is available for download below. You can import the layer definition file into KLayout by choosing File, then Load Layer Properties. Design examples for tri-layer metallization, deep trench, thermal isolation trenches, and the SEM imaging layer are also available. All of our tutorials are designed to match the Layer Definition file.
