With the deep trench option, trenches 250 microns deep are etched along the perimeter of the chip to allow for edge-coupling with optical fibers. Silicon nitride edge couplers can be more efficient than silicon edge couplers due to the lower index contrast of silicon nitride and the increased thickness of our silicon nitride layer compared to the standard silicon device layer. Additionally, the thick cladding oxide and BOX layers in our silicon nitride platform allow for highly efficient edge couplers. Edge couplers are available in the NanoSOI PDK. The trench is patterned around an 8.78 x 8.78 mm enclosed area, centered on the submitted GDSII design. A deep-etch process is then used to etch through the cladding, silicon nitride device layer, buffer oxide, and through 250 microns of the underlying silicon substrate. The remaining silicon handle wafer is diced with a saw to separate the chips. The etch and dice process occurs on all four sides of the chip.
