Rapid fabrication service for prototyping silicon photonic integrated circuits The NanoSOI Fabrication Service is a foundry service for the fabrication of photonic integrated circuits. Superior line-edge roughness, high throughput, and negligible stitching errors are guaranteed with the use of a state-of-the-art 100 keV electron-beam lithography system. Our anisotropic plasma etch process provides smooth sidewalls and low propagation loss. Optional standard process steps include oxide cladding deposition, metallization and deep trench etching to create passive and thermo-optic photonic devices with grating couplers or edge couplers. We also offer custom options including partial etch depths, oxide windows, and thermal isolation trenches. There are two options for accessing the NanoSOI Fabrication Service. Multi-project wafer (MPW) runs are scheduled once every six to eight weeks. Standard processes and immediate pricing are available for these runs. Dedicated runs are for projects requiring custom options. Timelines for these runs are flexible, and quotations are customized for each run. Rapid Fabrication Turnaround time from design submission to delivery as short as three weeks. High Performance Proven optical performance and low propagation loss. Multi-Project Wafer Runs Standard options include cladding oxide, metallization, and edge couplers. Dedicated Runs Fully customized to suit your needs with many options available. Easy-to-use online system Designs are submitted online using the NanoSOI Design Center. Design files are provided to us in Calma Graphics Data System II (GDSII) format, with database units of 1 nanometre. The latest design rules, layout tutorials, the process design kit, and an online design verification tool are all located at the NanoSOI Design Center. Process Design Kits (PDKs) are available for KLayout, and the Luceda Photonics Design Platform. The run schedule and pricing for multi-project wafer runs is also available online through the Design Center. We track our optical propagation loss using test structures on every multi-project wafer run. The test structures are comprised of 500 nm-wide silicon strip waveguides with 2.2 μm thick cladding oxide. Cut-back loss measurements are performed by varying the length of the waveguide, measuring the total insertion loss of each device, and performing a linear fit of loss versus waveguide length. The average propagation loss for fully-etched 220 nm SOI devices is shown here: Polarization | Straight Waveguide Loss | Curved Waveguide Loss TE | 1.2 dB/cm | 3.0 dB/cm TM | 1.7 dB/cm | 2.3 dB/cm Detailed measurement data, including spectral scans, can be provided by request.
