By IBM Research
A new Coursera specialization, Dataflow Architectures for AI: From Principles to Practice, is built for engineers who need to work across that range. Taught by Kaoutar El Maghraoui, a principal research scientist at IBM Research and adjunct professor of computer science at Columbia University, the six-course program covers execution models, compilation, memory systems, debugging, and performance modeling through hands-on labs. The specialization starts from a single PyTorch model. At the framework level it is the same nn.Module on every target. Once a compiler maps it onto hardware, the execution looks very different, and each stack supports its own set of operators, layouts, and graph transformations. A GPU runs the model as kernels across many parallel threads, with hardware-managed caches and specialized matrix units. A TPU maps the work onto systolic arrays, with the XLA compiler directing tiling and data movement. Cerebras spreads compute and more than 40 GB of on-chip SRAM across a full wafer. Groq relies on its compiler to schedule when each operation runs and when data moves. Spyre compiles the model into a dataflow graph, and its compiler decides layout and scratchpad placement while the runtime orchestrates transfers and launches. The details vary by product generation. The specialization treats dataflow execution as an architectural class with shared principles. Each concept is introduced in general terms before any specific system is discussed. Spyre is the main worked example because El Maghraoui's team works with it directly, but it is one of five systems compared throughout. The specialization is a sequence of six courses. Each course covers one layer of the stack, and each ends in a lab. Together they build up the accelerator landscape map one row at a time. Completing all six earns the professional certificate in AI Systems Performance Engineering. - Course 1 — The accelerator landscape: Domain-specific architectures, control-flow and dataflow execution, memory hierarchies, and programming models across all five systems. - Course 2 — Dataflow execution models: Nodes, edges, firing rules, and static and dynamic scheduling. A transformer attention block traced through Spyre and TPU. - Course 3 — Compilation for dataflow: TorchDynamo, AOTAutograd, and backend code generation. Fusion, tiling, and scheduling in XLA and the Spyre compiler. - Course 4 — Memory systems: Caches, scratchpads, and SRAM-only designs. How each memory hierarchy changes KV cache management for LLM inference. - Course 5 — Debugging across the dataflow stack: An eight-layer taxonomy of failures, including graph capture errors and scheduling deadlocks, DMA timeouts, and numerical issues. - Course 6 — Performance modeling and optimization: Roofline analysis adapted for software-managed memory, with scheduling measured as a third bottleneck alongside compute and memory. Every course culminates in a core lab that runs on Google Colab with standard PyTorch. Each lab also has an optional Spyre practice portion that runs on Spyre hardware. The labs are developed by Rashed Bhatti, PhD, a senior technical staff member at IBM Research and a contributing lab instructor for the specialization. Each takes 90 minutes to two hours, and students write and run their own code. In the first lab they build a benchmarking harness from scratch with torch.utils.benchmark and explain the CPU to GPU gap in terms of SIMT parallelism and HBM bandwidth. Later labs trace a transformer block with torch.fx, compare eager mode with torch.compile, read the PyTorch Profiler memory timeline during LLM inference, diagnose three planted bugs, and build a Roofline chart for an LLM workload. No proprietary tools are required for the core labs. In the optional Spyre practice portion, called the Dataflow Deep Dive, students in partnered programs run the same labs on Spyre hardware. There they work directly with the dataflow concepts from each course: They read the dataflow graph the Spyre compiler produces and catalog the fusions and data-movement edges it inserts, follow how tensors are tiled into sticks and placed in scratchpad memory, measure traffic between HBM and the scratchpads with hardware counters, and build a Roofline from those counters for a software-managed memory hierarchy. The deep dive is not required to finish the specialization or earn the certificate. The specialization is designed for intermediate to advanced learners, including graduate students in computer science or electrical engineering, compiler engineers, hardware architects, and ML practitioners who optimize workloads across hardware targets. Participants should be comfortable with intermediate Python and C/C++, familiar with CNN and transformer architectures, and grounded in basic computer architecture. Learners who complete the program receive a professional certificate in AI Systems Performance Engineering. The specialization is open for enrollment on Coursera.
